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Configurable Timing Parameters
FlexROM III gives you control over some of its timing parameters. If you are not a hardware type then
these options may not make much sense. Don’t worry about it. The default settings will almost always
work. These options are provided to enhance the emulator’s robustness in particularly noisy targets or
targets that violate some of our specs. Even in those rare cases, you should be able to make reasonably
well-informed selections based on the descriptions below and minimal help from your hardware engineer.
Throughout this section, we will be talking about control signals and timing requirements. To keep things
readable, we need to agree on some acronyms. The follow acronyms are commonly used when talking
about memory devices:
Acronym
CS
OE
WT
BHE
BLE
Tacc
Tcs
Toe
Twp
Tcr
Description
Chip Select
Output Enable
Write Enable
Byte High Enable
Byte Low Enable
Address Access Time
Chip Select Access Time
Output Enable Access Time
Write Pulse Width
Cycle Recovery Time
Notes
Enables the device when driven low
Enables the devices output buffers if CS is active
Enables a WRITE cycle if the CS is active
Selects D8-15 for any valid cycles
Selects D0-7 for any valid cycles
Time from address stable to valid data out
Time from CS enabled to valid data out
Time from OE enabled to valid data out
Time WT line is held active during a write cycle
Time between the end of a cycle and the beginning
of the next. A cycle ends when CS goes inactive
or both OE and WT go inactive. A cycle begins
when CS is active AND either OE or WT goes
active.
NOTE: It is somewhat of a misnomer to talk about a device’s ACCESS TIME. There really is not a single
access time spec. The device will provide data only after meeting ALL access time specs. Generally, when
we say a device has a ‘70ns access time’ we are referring the to Tacc spec which is usually equal to the Tcs
spec.
FlexROM III User’s Manual
21
Copyright ? 2001, TechTools
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